Temperature Dependence of Germanium Arsenide Field-Effect Transistors Electrical Properties ^†

Abstract

In this work, we report the fabrication of germanium arsenide ($GeAs$) field-effect transistors with ultrathin channel and their electrical characterizations in a wide temperature range, from $20$ to $280 \mathrm{K}$. We show that at lower temperatures, the electrical conduction of the $GeAs$ channel is dominated by the 3D variable range hopping but becomes band-type at higher temperatures, after the formation of a highly conducting two-dimensional (2D) channel. The presence of this 2D channel, limited to a few interfacial $GeAs$ layers, is confirmed by the observation of an unexpected peak in the temperature dependence of the carrier density per area at $\sim 75 \mathrm{K}$. Such a feature is explained considering a model based on a temperature-dependent channel thickness, corroborated by numerical simulations, that show excellent agreement with the experimental data.

1. Introduction

Recent interest in research on two-dimensional (2D) materials has led to the exploration of new classes of layered materials beyond graphene and transition metal dichalcogenides. Among these, the binary compounds of groups IV and V are assuming considerable importance since theoretical studies have proved their crystalline layered structures with orthorhombic ($Cmc{2}_1$ for $SiP$ and $Pbam$ for $Si{P}_2$ and $GeA{s}_2$) or monoclinic ($C2/m$ for $GeP$, $GeAs$, and $SiAs$) symmetries [1,2,3,4]. Particularly, $GeAs$ has been considered for possible optoelectronic applications and for its high in-plane anisotropy [5,6]. Figure 1a shows the $GeAs$ crystal layered structure, in which each $Ge$ atom is bonded to one $Ge$ atom and three $As$ atoms forming distorted $A{s}_6@G{e}_2$ octahedra [7]. Similar to TMDs, the $GeAs$ bandgap changes according to the number of layers. Numerical calculations and optical bandgap measurements, indicate that germanium arsenide indirect bandgap ranges from $~0.57-0.65 \mathrm{eV}$ for the bulk [8,9] to $1.6-2.1 \mathrm{eV}$ for the monolayer [10,11].

In this work, we report the fabrication of $12 \mathrm{nm}$ thick $GeAs$ back-gate field effect transistors through mechanical exfoliation and their electrical characterization in a four-probe configuration and in a range of temperatures from $20$ to $280 \mathrm{K}$. We find that at low temperature, the conduction is dominated by 3D variable range hopping but becomes band-type at higher temperatures. This change in the conduction mechanism is due to the formation of a highly conducting 2D channel close to the gate, confirmed by the observation of an unexpected peak in the temperature dependence of the carrier density per area at $\sim 75 \mathrm{K}$. The model is corroborated by numerical simulations that show an excellent agreement with the experimental data.

2. Results and Discussion

Figure 1b shows an optical image of a $12 \mathrm{nm}$ thick $GeAs$ flakes covered with eight $5 \mathrm{nm} \mathrm{Ni}/40 \mathrm{nm} \mathrm{Au}$ electrodes. Ultrathin $GeAs$ flakes were exfoliated from bulk $GeAs$ single crystals using a standard mechanical exfoliation method by adhesive tape. The flakes were transferred onto degenerately doped p-type silicon substrates, covered by $300 \mathrm{nm}$-thick ${\mathrm{SiO}}_2$. Electron-beam lithography were performed on selected flakes to obtain a Hall bar structure. Finally, electron-beam evaporation was used to deposit the metal electrodes [12].

Contacts 1 to 4 were used to perform a standard four probe electrical characterization in which the current ($I_{ds}$) is measured between the outers contact (1 and 4) and the voltage drop ($V_{xx}$) is measured between the inner contacts (2 and 3).

Figure 1c shows the output characteristic, i.e., the drain-source current as a function of the voltage drop between two inner contacts with the gate-source voltage ($V_{gs}$) as control parameter. It shows a linear behaviour that is not influenced by the gate potential which only changes the total conductance of the device. Moreover, it testifies the formation of ohmic contacts due to the alignment between the $\mathrm{Ni}$ Fermi level (work function $5.15 \mathrm{eV}$) below the valence band of $GeAs$. Figure 1d reports the transfer characteristic, i.e., the $g_{ds}-V_{gs}$ curve ($g_{ds}=I_{ds}/V_{xx}$ is the channel conductance) measured over a loop of the gate voltage. It shows a typical p-type behaviour mainly due to the presence of intrinsic defects such as $Ge$ vacancies, the interaction with the ${\mathrm{SiO}}_2$ gate dielectric and the oxidation of the topmost layers of the flake that would act as p-type dopants in the material and provide intragap states [1,2].

Figure 2a,b shows the temperature dependence of the electric behaviour of the device in the $20-280 \mathrm{K}$ temperature range. Particularly, from Figure 2a, we find that the conductance decreases lowering the temperature without any other apparent change in the behavior of the device and from a linear fit of the $I_{ds}-V_{xx}$ curves recorded at $V_{gs}=-20 \mathrm{V}$, we estimate the resistivity $\rho$ of the sample as a function of the temperature ($\rho =\mathrm{RW}/\mathrm{L}$, where $R$ is the resistance evaluated from the fit and $L=6$ and $W=2.7 \mathsf{\mu }\mathrm{m}$ are the channel length and width, respectively). The results of the fit are shown in the inset of Figure 2a in which a clear semiconductive behavior is observed. Figure 2b reports the transfer characteristic of the device in which we defined the FET channel conductance as:

$$g_{ds}=\frac{I_{ds}}{V_{xx}}=\left(\frac{W}{L}\right){\mu }_{FE} C_{ox} |V_{gs}-V_{th} { |}^{\alpha },$$

where ${\mu }_{FE}$ is the field-effect mobility; $C_{ox}={ϵ}_0·\frac{{ϵ}_{{\mathrm{SiO}}_2 }}{t_{{\mathrm{SiO}}_2}}=1.15·{10}^{-8} \mathrm{F}/{\mathrm{cm}}^2$ is the capacitance per unit area of the gate dielectric, where ${ϵ}_0=8.85·{10}^{-14} \mathrm{F}/{\mathrm{cm}}^2$, ${ϵ}_{{\mathrm{SiO}}_2}=3.9,$ and $t_{{\mathrm{SiO}}_2}=300 \mathrm{nm}$ are the vacuum permittivity, the ${\mathrm{SiO}}_2$ relative permittivity, and thickness, respectively; $V_{th}$ is the threshold voltage; and $\alpha \ge 1$ is a dimensionless parameter, which accounts for a possible $V_{gs}$-dependence of the mobility [13]. In order to have a fair comparison with the values of $\rho$ obtained from $g_{ds}-V_{xx}$ curves at $V_{gs}=-20 \mathrm{V}$, we performed linear fit of the transfer characteristics in a small interval around $V_{gs}=-20 \mathrm{V}$ in which we can consider $\alpha =1$. From the fit, we can extrapolate the mobility at each temperature as shown in the inset of Figure 2b. We find a quadratic dependence, ${\mu }_{FE} ~ T^2$, pointing towards a mobility dominated by Coulomb scattering due to ionized impurities [14]. A deeper analysis of the $\rho$ versus $T$ graph, shown in the inset of Figure 2a reveals that the electrical conduction follows two different mechanisms at low and high temperature, respectively. Indeed, we notice that the best fitting of the experimental data at low temperature is obtained using the variable range hopping conduction (VRH). According to VRH theory, the relation between $\rho$ and $T$ can be expressed as [15]:

$$\rho \left(T\right)={\rho }_0 exp{\left(\frac{T_0}{T}\right)}^{\frac{1}{n+1}} ,$$

where ${\rho }_0$ depends on the square root of $T$, $T_0$ is a constant, and n indicates the dimensionality of the system [16].

Figure 2c shows $\ln (\rho \ast T^{-\frac{1}{2}}$) as function of $T^{-\frac{1}{4}}$ in the range of $20$–$80 \mathrm{K}$. The linearity demonstrates that the conduction is bulk type (3D) for $T<80 \mathrm{K}$, i.e., it occurs through the entire flake constituted of $\sim 20$ atomic layers. Figure 2d shows the trend for $T>180 \mathrm{K}.$ We observe an exponential increase with the inverse of temperature that indicates that the thermal excitation of carriers (holes) to the valence band leads to a band conduction regime, $\rho \propto exp\left(E_A/kT\right)$, as expected after the formation of a highly conductive 2D channel in the $GeAs$ transitor.

In order to try to explain this strange passage from a bulk to a 2D conduction, we calculate the carrier density per unit area $n$ (in ${\mathrm{cm}}^{-2}$) as a function of the temperature. Indeed, having computed ${\mu }_{FE} \left(T\right)$ and $\rho \left(T\right)$ at each of the considered temperatures, $n$ can be obtained from the relation:

$$n\left(T\right)=1/\left(q\rho \left(T\right){\mu }_{FE} \left(T\right)\right) ,$$

where $q$ is the electron charge. Figure 3a shows that $n\left(T\right)$ exhibits an unexpected and pronounced peak at $T~75 \mathrm{K}$, followed by a smoother increase for $T>150 \mathrm{K}$. In a doped three-dimensional semiconductor, the carrier density would show a different temperature behavior [14]. Specifically, an initial rapid increase due to the ionization of dopant atoms by thermal energy (freeze-out region, up to $~150 \mathrm{K}$ for medium-doped $Si$) would be followed by a plateau over a wide temperature range when complete ionization is reached (extrinsic region, $~150-500 \mathrm{K}$ for medium-doped $Si$), and would finally evolve in an exponential increase at higher temperatures due to intrinsic generation of electron–hole pairs (intrinsic region). To explain both the reported anomalous behavior and the modification from a bulk to a 2D conduction due to increasing temperature, we propose a model that considers a temperature-dependent thickness of the channel in which most of the conduction occurs. Indeed, we notice that the 2D carrier density per unit area can be expressed as $n\left(T\right)=\phi \left(T\right)\tau \left(T\right)$ where $\phi$ is the carrier density per unit volume in ${\mathrm{cm}}^{-3}$ and $\tau$ is the thickness of the conducting channel. The current in the $GeAs$ flake is due to carriers injected from the $\mathrm{Ni}$ contacts that overcome a potential barrier, $E_A$, between the contacts and the channel region. Therefore, $\phi \left(T\right)$ in the region between the inner contacts can be expressed as [17]:

$$\phi \left(T\right)=A exp\left[-E_A/kT\right] ,$$

where $k$ is the Boltzmann constant and $A$ is a proportionality constant that can be considered as a fitting parameter of the model.

At low temperature ($<80 \mathrm{K}$), there is a limited amount of carriers as well as high intralayer resistance that suppresses the vertical transport with respect to the in-plane one [18,19]. In this regime, conduction occurs mainly through the layers in closer contact with the metal leads (especially the topmost ones) and the gate electric field controls the entire flake thickness. With raising temperature, defect ionization, and injection from the contacts increase. The new available carriers, pushed by the applied gate voltage and the favorable vertical band bending toward the interface with the gate dielectric, form a 2D channel, which becomes more and more conductive with the rising temperature. This channel now screens the gate field, and any variation of the gate voltage affects mainly the bottommost layers of the flake. In this regime, the conduction is dominated by a few atomic $GeAs$ layers closer to the gate, i.e., the effective conducting thickness $\tau \left(T\right)$ controlled by the gate is reduced.

To test the model, with an appropriate choice of $\phi \left(T\right)$ and $\tau \left(T\right)$, we computed $n\left(T\right)$ obtaining an excellent agreement with the experimental data, as shown in Figure 3a, where we display $n\left(T\right)$ at $V_{gs}=-20 \mathrm{V}$. The carrier density per volume $\phi \left(T\right)$, given by Equation (4), is shown by the red line of Figure 3b, with $E_A$ obtained as fitting parameter. For $\tau \left(T\right)$, we used a step-like function, $\tau \left(T\right)=A/\left(1+exp\left(B\ast T\right) \right)+C$, represented by the black curve shown in Figure 3b, in which $A$ is the initial thickness of the whole flake, i.e., $~ 12 \mathrm{nm}$, $C$ is the thickness of a single $GeAs$ layer ($0.6 \mathrm{nm}$), and $B$ is a fitting parameter used to simulate a smooth transition in the $70-150 \mathrm{K}$ range. Finally, the model is further corroborated by the estimation of the Debye screening length $L_D=\sqrt{\frac{ϵ{ϵ}_{0}kT}{q^2\phi }}$, that gives the length over which the electric field strength drops by a factor $1/e$ (here $ϵ=8$ is the dielectric constant at room temperature of the material [20]). From our data, we estimate $L_D ~ 0.4 \mathrm{nm}$ at room temperature, confirming that the gate electric field is substantially screened in the layer closer to the gate.

3. Conclusions

We fabricated back-gate field effect transistors with ultrathin $GeAs$ films and investigated their electrical properties over a wide temperature range, from $20$ to $280 \mathrm{K}$. We found a p-type behaviour with temperature increasing conductivity. We find that the conduction is dominated by the 3D variable range hopping at lower temperatures but becomes band-type at higher temperatures, when a highly conducting 2D channel is formed. We observed that the carrier density in $GeAs$ flakes depends on temperature with a pronounced and broad peak around $75 \mathrm{K}$. We proposed a model based on a temperature-dependent channel thickness to explain such an anomaly that shows an excellent agreement with the experimental data.